Peak Dynamic Power Estimation of FPGA-mapped Digital Designs

The Peak Dynamic Power Estimation (PDPE) problem involves finding input vector pairs that cause maximum power dissipation (maximum toggles) in circuits. The PDPE problem is essential for analyzing the reliability and performance of digital circuits prior to fabrication. This paper proposes a methodology for solving the PDPE problem on circuits mapped onto Field Programmable Gate Arrays (FPGAs). An FPGAmapped circuit comprises of a collection of Look Up Tables (LUTs) connected by interconnects. Hence, the input to the proposed algorithm is an LUT-level netlist (similar to gate-level netlists that are generated in the ASIC design flow). To the best of our knowledge, this is the first such technique reported in the literature for the PDPE on LUT-level netists. The proposed methodology was experimented on the LUT-level netlists of ISCAS’85 combinational benchmark circuits. A maximum toggle estimate improvement of 32.05% is observed when compared to a random estimation method on the same. The paper also presents interesting observations on the non-correlation between optimizations at the gate level and the LUT level netlists. These suggest that low-power design techniques applied at higher levels of design abstractions need not necessarily result in a design that is power aware at the LUT level.