LambdaRank acceleration for relevance ranking in web search engines (abstract only)

  • Jing Yan ,
  • Ning-Yi Xu ,
  • Xiong-Fei Cai ,
  • ,
  • Yu Wang ,
  • Rong Luo ,
  • Feng-Hsiung Hsu

Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays |

Published by ACM

论文与出版物

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This paper describes a FPGA-based hardware acceleration system for LambdaRank algorithm. LambdaRank Algorithm is a Neural Network (NN)-based learning to rank algorithm. It is intensively used by web search engine companies to increase the search relevance. Since i) the cost function for the ranking problem is much more complex than that of traditional Back-Propagation(BP) NNs, and ii) no coarse-grained parallelism exists, LambdaRank is hard to be efficiently accelerated by GPU or computer clusters. We presents a FPGA-based accelerator solution to provide high computing performance. A compact deep pipeline is proposed to handle the complex computing in the batch updating. The area scales linearly with the number of hidden nodes in the NN model. We also carefully design a data format to enable streaming consumption of the training data from host computer. The accelerator shows up to 24.6 speedup compared with the pure software implementation on datasets from a commercial search engine.