A Genetic Approach to Gateless Custom VLSI Design Flow

In this work, we propose a novel technique for evolving transistor netlists from truth table descriptions of arbitrary digital circuits. The proposed methods incorporate the effective use of genetic algorithms (GAs). In typical semi-custom and custom design flows, logic optimization is done at the gate level after Boolean translation of the input truth table. The final transistor netlist is then deduced from the simplified gate logic to be laid out on a chip. However transistor level optimizations after the Boolean simplification step would still not lead to the minimum number of transistors. This final optimization level is non-existent in present custom design flows. This work aims to address this need. A salient feature of the proposed technique is the bypassing of gate level representation and optimization in the VLSI design flow. We provide genetic methods to directly optimize truth table inputs using transistor level simplification. This eliminates the intermediate gate level optimization step and provides optimized transistor netlists which could be used for dynamic library cell generation for custom and semi-custom designs on the fly.