The 48th International Symposium on Microarchitecture happened last December and brought interesting discussions to bear. On the technical side, there were three very inspiring keynote speeches and a number of great presentations. The regular paper presentations were also very diverse, covering all the way from cache design, memory prefetching, and memory optimization, to hardware security, energy efficiency and hardware accelerators.
The first keynote (opens in new tab) was by Prof. Jan Rabaey from UC Berkeley, who discussed the implications of wearable devices. His main points were that pervasive wearables require ubiquitous, distributed and personal information processing, and this can only be achieved by pushing the limits of miniaturization, energy efficiency and wireless distributed systems design. He cited some of the recent work in neuro-inspired architectures.
The second keynote (opens in new tab) was by Prof. Todd Austin from Univ. of Michigan, whose speech covered the end of silicon scaling, as I discussed in an article (opens in new tab) a few months ago. Prof. Austin discussed customization in addition to parallelism as mechanisms to address the upcoming challenges. His main point was that, for these challenges to be overcome, hardware design needs to be much cheaper than it is today (100 times cheaper to bring a design to market). He suggested 5 approaches to accomplish this: much bigger improvements from architectural innovation (e.g., speculative parallelizing compilers, application specific processors), significant cost reductions to design custom hardware (e.g., better tools and benchmarks), use of open-source hardware, more widely-applicable custom hardware designs (module reuse and auto-tuning), and reduction in manufacturing custom hardware (e.g., modular 3D stacking).
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The third keynote (opens in new tab) was by J. Thomas Pawlowski, Chief Technologist and Fellow from Micron. He reminded us that memory offers the densest transistors, and walked us through transistor scaling trends. With the multicore era, the pressure for higher memory bandwidth has increased, and the HMC (hybrid memory cube) will offer 41 times higher memory bandwidth than regular DIMMs. He touched on emerging memory technologies, and indicated the new non-volatile memories including Intel-Micron’s new 3D XPoint™ will fit between DRAM and NAND flash in the memory hierarchy. He also talked about processing in memory and Micron’s Automata Processor, and further abstraction of storage and memory with the new HMC protocol.
Finally, on the organizational side, a presentation by Prof. Moin Qureshi (opens in new tab)explained his very innovative paper selection process, which included a revision-based model that allowed authors of about 100 top papers to provide edits in-line with their papers instead of through a separate rebuttal. According to the statistics he presented, the process was successful in improving paper quality and resulted in more positive outcomes for the revised papers compared to a simple rebuttal. Overall, MICRO was an energizing experience. In addition to the great program, Hawaii was just the right location to bring that extra jolt of energy to it. Discussing computer architecture in a comfortable temperature while hearing the tropical birds chirp in the background was a great way to conclude the year!
Karin Strauss (opens in new tab) is a researcher at Microsoft Research and an Associate Affiliate Professor at University of Washington. Her research interests include computer architecture and systems, specifically emerging memory technologies and systems tailored to best leverage them, hardware support for machine learning, in-cell DNA computation, and DNA storage.
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